Voltage controlled oscillators (VCOs) typically generate a frequency output based on an analog voltage input. Such oscillators are widely known in the art of integrated circuit manufacture. One particular implementation that has attained wide acceptance is known as the ring oscillator. By way of example, ring oscillators are described in U.S. Pat. Nos. 3,931,588; 4,072,910 and 4,891,609.
In a ring oscillator, the current output of each stage takes a finite time to charge or discharge the input capacitance of a following stage to its threshold voltage. The number of inverting stages is odd and the stages are cascaded in a loop so that at a certain frequency, a 180.degree. phase shift is imparted to signals passing around the loop. Provided the loop gain is large enough, the signals become non-linear and square-wave oscillations are produced. Such oscillations can be used for a variety of applications. For example, a ring oscillator based VCO can be employed by a phase-locked loop (PLL) circuit. As is well known, PLL circuits provide an output signal that is substantially the same frequency and phase as an input reference signal.
Voltage controlled oscillators are designed to operate at a predetermined frequency based upon an applied control voltage at a VCO input, wherein a fifty percent duty cycle is conventionally derived from the VCO operating frequency. The fifty (50%) percent duty cycle clock is typically equal to one-half the operating frequency of the VCO and is generated by passing the output signal of the VCO through a divide by two logic block. Thus, in order to obtain a fifty percent duty cycle at, for example, 40 MHz, the VCO must operate at 80 MHz. Implementation of this conventional approach becomes more and more difficult as operating frequencies rise. Additionally, with this approach the frequency output and frequency gain factor of the VCO remain sensitive to process and temperature variations.
CMOS voltage controlled ring oscillators of the recent art have been designed with individual control of current at each delay stage of the oscillator ring. An output of one of the stages drives a CMOS logic gate which is usually an inverter with an input threshold equal to about one-half a power supply voltage V.sub.DD. The voltage into the logic gate has an amplitude substantially less than this supply voltage. The signal typically does not have sharp edges, and its center point varies with process tolerances, supply voltage and operating temperature. Thus, the waveform at the output of one or more serial logic gates has steep edges, but a variable duty cycle.
Often it is desirable that a ring oscillator's output be symmetrical with a constant, fifty (50%) percent duty cycle. Hence, a need exists for a novel ring oscillator circuit that provides a high frequency symmetrical output waveform having a constant, fifty (50%) percent duty cycle. The oscillator circuit described herein satisfies this need.